| Lab Schedule and Resources | ||
|---|---|---|
| Class Date | Topics | Resources |
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| Week 1 |
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| Week 2 |
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| Week 3 |
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| Week 4 | Integrated Circuit - Parametrics | |
| Week 5 | VHDL - Logic Circuits | |
| Week 6 | No Lab - Test Week | |
| Week 7 | Logic Reduction and Synthesis | |
| Week 8 | VHDL Logic Synthesis | |
| Week 9 | VHDL Logic Synthesis | |
| Week 10 | D Flip-Flop | |
| Week 11 | No Lab - Test Week | |
| Week 12 | VHDL Registers | |
| Week 13 | Finite State Machine - Brute Force | |
| Week 14 | Finite State Machine - Behavioral | |