CE 1911 - Spring 2022

Class Schedule and Notes
Class Date	Topics	Pre-Work	Resources
W1 - C1	Topics	Pre-Work	Resources	Review CE 1901	Intro and Overview video	Logic Review Number Systems Binary Addition and Subtraction Number Systems Practice Program
W1 - C2	Logic -> Latches 3.1 - 3.2.2	DC Characteristics video Digital Signals video Latches video
W1 - LAB Lecture	Flip-Flops xx - xx	Flip-Flop Basics video Flip-Flop Enhancements video	Tristate Inverter
W1 - C3	Flip-Flops xx - xx	Flip-Flop Circuit Operation video Flip-Flop Circuits video	D-FF Spec Shift Register Spec Counter Spec Register File Spec
W2 - C1	Timing xx - xx	Logic Timing video Flip-Flop Timing video Register Transfer Architecture video Flip-Flop Timing Analysis video
W2 - C2	HDL Concepts	FPGA Design Flow video VHDL Review video Synchronous VHDL video	with-select when-else if-else case VHDL Operator Precedence
W2 - C3	Synchronous HDL xx - xx	HDL Flip-Flops video Testbench Development video HDL Registers video	ff1 ff1_tb ff1_8 ff1_8_tb ff1_N ff1_N_tb
W3 - C1	Synchronous HDL xx - xx	HDL Types video HDL Counters video HDL Register Files video	VHDL Types VHDL Type Attributes VHDL Type Conversion VHDL Best Practices counter_M.vhdl counter_M_tb.vhdl
W3 - C2	State Machines xx - xx	State Machine Intro video State Diagrams video State Machine Design video	State Machine Design Process
W3 - C3	State Machines xx - xx	State Machine Design Examples video
W4 - C1	State Machines xx - xx	State Machine Encoding video State Machine Encoding Example video	4b Johnson and Gray Codes
W4 - C2		Test 1 Review	Test 1 Topics
W4 - C3		Test 1
W5 - C1	HDL FSMs xx - xx	HDL FSM Intro video Enumerated States video	Adding States to simulation
W5 - C2	HDL FSMs	HDL FSM Examples video
W5 - C3	HDL FSMs xx - xx	HDL FSM Timers and Counters video HDL State Machine Encoding video
W6 - C1	Memories 5.5	Memory Intro video Read Only Memory - ROM video Sync Random Access Memory - SRAM video	SRAM Spec
W6 - C2	Memories	Sync Dynamic RAM video Flash video	DRAM Spec Flash Spec
W6 - C3	Break
W7 - C1	HDL Memories 5.5	HDL Memory Intro video HDL ROM video HDL ROM w/ MegaWizard video	MIF File Format
W7 - C2	HDL Memories	HDL SRAM video HDL SRAM w/ MegaWizard video
W7 - C3	Single Cycle Processor 7.1 - 7.3	Single Cycle Processor Intro video Single Cycle Processor ALU video Single Cycle Processor Instructions video
W8 - C1	Single Cycle Processor	Single Cycle Processor DataPath video Single Cycle Processor Operation video Single Cycle Processor Control video
W8 - C2	Single Cycle Processor	Single Cycle Processor Examples video Single Cycle Processor Implementation video
W8 - C3	FSMD	Algorithmic State Machine Diagrams video FSM w/ DataPath video
W9 - C1	FSMD	FSMD Example - Fibonacci video FSMD Example - Multiplier video
W9 - C2		Open - Project Work
W9 - C3	Advanced Testbenches	File I/O video Verification Automation video
W10 - C1		Open - Project Work
W10 - C2		Open - Project Work
W10 - C3		Test 2 Review
Finals Week	011 T 5/17 8-10 DH229 031 W 5/18 2-4 S210	Test 2	Test 2 Topics