|
Common Resources |
|
|
W1 - C1 |
No Class |
|
|
W1 - C2 |
Design Flow |
|
|
W1 - C3 |
VHDL Review |
|
|
W2 - C1 |
Verification |
|
|
W2 - C2 |
Basic Logic Blocks |
|
|
W2 - C3 |
Finite State Machines |
|
|
W3 - C1 |
FSMs with Datapath |
|
|
W3 - C2 |
FPGA Architecture |
|
|
W3 - C3 |
MAX10 Memory |
|
|
W4 - C1 |
|
|
|
W4 - C2 |
PLLs and Multiplies |
|
|
W4 - C3 |
|
|
|
W5 - C1 |
Test 1 Review |
|
|
W5 - C2 |
Catch-up, help |
|
|
W5 - C3 |
Test 1 |
|
|
W6 - C1 |
NIOS II Intro |
|
|
W6 - C2 |
NIOS II I/O |
|
|
W6 - C3 |
NIOS II Character Buffer |
|
|
W7 - C1 |
NIOS II Pixel Buffer |
|
|
W7 - C2 |
NIOS II Peripherals |
|
|
W7 - C3 |
NIOS II Interrupts |
|
|
W8 - C1 |
MAX10 ADC |
|
|
W8 - C2 |
Accelerometer |
|
|
W8 - C3 |
Serial Communications |
|
|
W9 - C1 |
Project Work |
|
|
W9 - C2 |
Project Work |
|
|
W9 - C3 |
Project Work |
|
|
W10 - C1 |
Test 2 Review |
|
|
W10 - C2 |
Project Work |
|
|
W10 - C3 |
Test 2 |
|
|