CPE 1500 - Spring 2025

Class Schedule and Notes
Class #	Class Date	Topics	Notes	Resources
		Topics	Notes	Resources	VHDL Best Practices - CPE1500
1	W1 - C1	Holiday	No Class
2	W1 - C2	Introduction	Intro Digital Systems Project Expectations Stategies for Success Signals Systems
3	W1 - C3	The Digital Abstraction	Voltage Supplies Ones and Zeros The Bit video Bits and Bytes video Binary Number Basics video
4	W2 - C1	Binary Numbers	Unsigned Binary Numbers video Unsigned Binary Number Addition video Signed Binary Numbers video Signed Binary Number Addition video Binary Number Subtraction video Hexadecimal Numbers video
5	W2 - C2	Boolean Logic	Basic Logic video Boolean Logic video Boolean Logic Laws video
6	W2 - C3	Digital Logic	Digital Logic Basics video Digital Logic Gates video	Digital Logic Precedence
7	W3 - C1	RC Introduction	Resistor Circuits video Capacitor Circuits video R-C Circuits video
8	W3 - C2	CMOS Circuits	CMOS Transistor Basics video CMOS Inverter video CMOS Logic Circuits (Gates) video
9	W3 - C3	CMOS Performance	Logic Levels video CMOS Timing Characteristics video CMOS Logic Area video CMOS Logic Power video
10	W4 - C1	Digital Logic Evaluation	Truth Tables video Digital Logic Evaluation - Expressions video Digital Logic Evaluation - Gates video
11	W4 - C2	Digital Logic Timing	Gate Level Signal Diagrams video Digital Logic Timng Analysis video Digital Logic Timng Glitches video
12	W4 - C3	HDL Introduction	Hardware Description Languages video VHDL video VHDL File Structure video VHDL Signals video VHDL Entity video VHDL Architecture video Behavioral VHDL video Structural VHDL video	VHDL Types - CPE 1500 VHDL Logic Operators Vector Manipulation
13	W5 - C1	VHDL Simulation Logic	VHDL Development Process for Logic video Examples video
14	W5 - C2	Logic Reduction	Logic reduction using the Boolean Laws video Logic reduction using Bubble Pushing video
15	W5 - C3	Logic Reduction	Karnaugh Maps video Logic Reduction using K-maps - SOP form video Logic Reduction using K-maps - POS form video
16	W6 - C1	Test 1 Review	Test 1 Topics
17	W6 - C2	Open
18	W6 - C3	Test 1	Test 1 Topics
19	W7 - C1	Logic Synthesis	Synthesis - Direct Implementation video
20	W7 - C2	Logic Synthesis	Multiplexor video Synthesis - Multiplexors video
21	W7 - C3	Logic Synthesis	VHDL - Simple Constructs video Synthesis - VHDL video	others with - select when - else mux_4 mux_4b mux_4_tt mux_4c odd_even_simple sign_extend_4_8 led_sensor
22	W8 - C1	More Combinational Logic	Decoders video Encoders video Comparators video Input Shifters video
23	W8 - C2	Logic Synthesis VHDL	VHDL Encoders video VHDL Decoders video VHDL Shifters video
24	W8 - C3	Adders	Full Adder video Ripple Carry Adder video Carry Lookahead Adder video Subtractor video
		Spring Break
25	W9 - C1	ALU	Arithmetic Logic Unit video
26	W9 - C2	Logic Synthesis VHDL	VHDL Numeric Types video VHDL Type Conversion video VHDL Adders / Subtractors video VHDL Comparators video Using Generics video	VHDL Type Conversion Map
27	W9 - C3	Sequential Logic	Clock Systems video Sequential Circuits video Latches video Flip Flop Basics video
28	W10 - C1	Design w/ Flip-Flops	Flip Flop Enhancements video Flip Flop Timing video Flip Flop Circuit Analysis video
29	W10 - C2	Registers & Counters	Registers video Register Files video Counters video
30	W10 - C3	RTL Analysis	Register Transfer Level (Logic) video RTL Timing Analysis video RTL Timing Verification video
31	W11 - C1	VHDL Process VHDL Flip-Flops	VHDL Process video VHDL Process Constructs video VHDL Flip Flop Template video VHDL Flip Flop Examples video	if - else case
32	W11 - C2	Test 2 Review	Test 2 Topics
33	W11 - C3	Test 2	Test 2 Topics
34	W12 - C1	Test Benches	VHDL Testbench Coding video VHDL Testbench Simulation video VHDL DE10 Implementation video	Additional VHDL Simulation Constructs DE10 Lite QSF file
35	W12 - C2	VHDL Registers VHDL Counters	VHDL Data Registers video VHDL Shift Registers video VHDL Register Files video VHDL Counters video
36	W12 - C3	Finite State Machines	State Machine Intro video State Diagrams video State Machine Design video	State Machine Design Process
37	W13 - C1	Finite State Machines - cont'd	State Machine Design Examples video State Machine Encoding video State Machine Encoding Examples video	4 bit Gray and Johnson Encoding
38	W13 - C2	VHDL FSMs	VHDL FSM Intro video Enumerated States video	Adding States to the Simulation
39	W13 - C3	VHDL FSMs cont'd	VHDL FSM Examples video
40	W14 - C1	VHDL FSMs cont'd
41	W14 - C2	Memory	Memory Intro video ROM SRAM DRAM FLASH
42	W14 - C3	Memory cont'd	Memory Architecture video
43	W15 - C1	VHDL Memory	VHDL Memories - Mux Based VHDL Memories - Flip-Flop Based VHDL Memories - Inferred
44	W15 - C2	open
45	W15 - C3	Final Review	Final Topics
	T 5/13 8:00 AM	Final	Final Topics