ELE 3510 - Spring 2024

Class Schedule and Notes
Class Date	Topics	Pre-work	Resources
	Topics	Pre-work	Resources	Common Resources	C Programming SW Tools Embedded Systems Logic Systems
W1 - C1	No Class
W1 - C2	Semiconductors	Intro Semiconductor Basics	Coding Ethics Semiconductor Parameters
W1 - C3	Integrated Circuit Devices	PN Junction Diodes MOS Enhancement Mode Transistor MOS Parametrics	IC Processes IC Lithography Planer CMOS Processing FinFET Processing Clean Room Video 1 Clean Room Video 2 IC Layout
W2 - C1	MOS Circuits	MOS Circuit Characteristics CMOS Inverter
W2 - C2	CMOS Circuits	CMOS Circuits
W2 - C3	CMOS Circuits	CMOS Area CMOS Timing CMOS Power CMOS Design Tradeoffs
W3 - C1	Logic Review	Power / Power Disribution Clocks / Clock Distribution Reset_Bar Power/Clock Gating and DVFS
W3 - C2	System Concepts	Combinatorial Logic Sequential Logic Hierarchical Design Design Reuse Domain Crossing Mixed Signal Design Resource Management
W3 - C3	VHDL Review	VHDL VHDL Review VHDL Processes Flip-Flop Construct Generics VHDL Best Practices	with-select when-else if-else case VHDL Types VHDL Type Attributes VHDL Type Conversion VHDL Operator Precedence VHDL Special Functions VHDL 2008 Specification
W4 - C1	Design Flow	System Design Process FPGA Design Flow	FPGA Pin Assignments
W4 - C2	Verification	Verification Testbench Basics	Testbench File I/O Testbench Automation ATE Testing
W4 - C3	Basic Logic Blocks	Registers Counters Clock Dividers
W5 - C1	Memory	Memories ROM SRAM DRAM FLASH
W5 - C2	Memory	Memory Logical View Memory Architecture VHDL Memories	ROM Constants
W5 - C3	State Machines / Diagrams	State Machines State Diagrams Optimized State Diagrams
W6 - C1	Finite State Machines	Simple FSMs Counter Based FSMs	FSM Encoding
W6 - C2	FSMs with Datapath	ASM Charts FSMD
W6 - C3	No class
W7 - C1	Single Cycle Processor - PIPELINED	Pipelined SCP
W7 - C2	Single Cycle Processor - PIPELINED
W7 - C3	Application VGA - HDL	VGA Basics VGA Driver HDL VGA Lab Note	VGA_drvr.vhdl VGA 10x4 testbench VGA 640x480 DE10 Implementation VGA 1280x1024 DE10 Implementation Display timing website
W8 - C1	Test 1 Review	Test 1 Topics
W8 - C2	Catch-up, help
W8 - LAB	Test 1
W8 - C3	No Class
	Spring Break
W9- C1	FPGA Architecture	FPGA Basics MAX10 Architecture	MAX10 Overview MAX10 Data Sheet MAX10 Architecture Handbook
W9 - C2	MAX10 Memory	MAX10 Memory Operation MAX10 Memory Configurations MAX10 Memory HDL	MAX10 Memory User Flash MIF File MAX10 Ram/Rom Guide MAX10 Flash Guide MAX10 FIFO Guide MAX10 Ram based Shift Register Guide
W9 - C3	PLLs and Multiplies	PLL Basics MAX10 PLL MAX10 PLL MegaWizard MAX10 Multiplier	MAX10 PLL Guide MAX10 Multiplier Guide
W10 - C1	Debug	SignalTap	SignalTap Reference
W10 - C2	NIOS II Intro	Nios II Processor Nios II Example	NIOS II Embedded Design Handbook NIOS II Processor Guide NIOS II Software Guide NIOS II Debug Guide
W10 - C3	NIOS II I/O	Nios II I/O
W11 - C1	NIOS II Character Buffer	Character Buffer Intro Character Buffer Hardware Character Buffer Software	Video IP Guide
W11 - C2	NIOS II Pixel Buffer	Pixel Buffer Intro Pixel Buffer Hardware Pixel Buffer Software	Embedded Peripherals Guide SDRAM Spec
W11 - C3	NIOS II Peripherals	Parallel I/O Interval Timer System ID	Embedded Peripherals - PIO Embedded Peripherals - Interval Timer Embedded Peripherals - System ID
W12 - C1	NIOS II Interrupts	Interrupts Interrupts Example	nios_interrupts_updown.c nios_interrupts_updown_2.c Exception Handlers
W12 - C2	MAX10 ADC	ADC Review Max10 ADC Max10 ADC - NIOS Example Max10 ADC - Toolkit Example	DE10 Lite ADC Warning MAX10 ADC Guide
W12 - C3	Accelerometer	Accelerometer Intro Accelerometer- NIOS Example	ADXL 345 (accelerometer) Spec
W13- C1	Serial Communications	SPI Review NIOS SPI Example	Embedded Peripherals - SPI
W13 - C2	Project Work
W13 - C3	Project Work
W14 - C1	Project Work
W14 - C2	Project Work
W14 - C3	Project Work
W15 - C1	Test 2 Review	Test 2 Topics
W15 - C2	Open
W15 - C3	Test 2