ELE 3510 - Fall 2025

Class Schedule and Notes
Class #	Class Date	Topics	Pre-work	Resources
		Topics	Pre-work	Resources	Common Resources	C Programming SW Tools Embedded Systems Logic Systems
1	W1 - C1	No Class
2	W1 - C2	Semiconductors	Intro Semiconductor Basics	Coding Ethics Semiconductor Parameters
3	W1 - C3	Integrated Circuit Devices	PN Junction Diodes MOS Enhancement Mode Transistor MOS Parametrics	IC Processes IC Lithography Planer CMOS Processing FinFET Processing Clean Room Video 1 Clean Room Video 2 IC Layout
4	W2 - C1	MOS Circuits	MOS Circuit Characteristics CMOS Inverter
5	W2 - C2	CMOS Circuits	CMOS Circuits CMOS Area
6	W2 - C3	CMOS Circuits	CMOS Timing CMOS Power CMOS Design Tradeoffs
7	W3 - C1	Logic Review	Power / Power Disribution Clocks / Clock Distribution Reset_Bar Power/Clock Gating and DVFS
8	W3 - C2	System Concepts	Combinatorial Logic Sequential Logic Hierarchical Design Design Reuse Domain Crossing Mixed Signal Design Resource Management	Digital Logic Precedence
9	W3 - C3	VHDL Review	VHDL VHDL Signals VHDL Entity VHDL Architecture Behavioral VHDL Structural VHDL Concurrent VHDL Sequential VHDL Class Video - do this with me	with-select when-else if-else case VHDL Types VHDL Type Attributes VHDL Type Conversion VHDL Operator Precedence VHDL Special Functions VHDL 2008 Specification
10	W4 - C1	VHDL Review - cont'd	VHDL Signal Types VHDL Processes Flip-Flop Construct VHDL Compile Time Calculations Generics VHDL Constants VHDL Best Practices	VHDL Best Practices
11	W4 - C2	Design Flow	System Design Process FPGA Design Flow	FPGA Pin Assignments
12	W4 - C3	Verification	Verification Testbench Basics	Testbench File I/O Testbench Automation ATE Testing
13	W5 - C1	Basic Logic Blocks	Multiplexors Demultiplexors Registers Register Files Adders/Subtractors
14	W5 - C2	Basic Logic Blocks	Counters Clock Dividers
15	W5 - C3	Memory	Memories Memory Logical View Memory Architecture VHDL Memories - Mux Based VHDL Memories - Flip-Flop Based VHDL Memories - Inferred VHDL Memories - Mega Wizard	ROM SRAM DRAM FLASH VHDL ROM Constants
16	W6 - C1	State Machines / Diagrams	State Machines State Diagrams Optimized State Diagrams
17	W6 - C2	Finite State Machines	Simple FSMs Counter Based FSMs	FSM Encoding
18	W6 - C3	FSMs with Datapath	ASM Charts FSMD
19	W7 - C1	Single Cycle Processor	Single Cycle Processor Intro Single Cycle Processor ALU Single Cycle Processor Instructions
20	W7 - C2	Single Cycle Processor	Single Cycle Processor DataPath Single Cycle Processor Operation Single Cycle Processor Control
21	W7 - C3	Single Cycle Processor	Single Cycle Processor Examples Video Single Cycle Processor Implementation
22	W8 - C1	Test 1 Review	Test 1 Topics
23	W8 - C2	Catch-up, help
24	W8 - C3	Test 1
25	W9- C1	FPGA Architecture	FPGA Basics MAX10 Architecture	MAX10 Overview MAX10 Data Sheet MAX10 Architecture Handbook
26	W9 - C2	MAX10 Memory	MAX10 Memory Operation MAX10 Memory Configurations MAX10 Memory HDL	MAX10 Memory User Flash MIF File MAX10 Ram/Rom Guide MAX10 Flash Guide MAX10 FIFO Guide MAX10 Ram based Shift Register Guide
27	W9 - C3	PLLs and Multiplies	PLL Basics MAX10 PLL MAX10 PLL MegaWizard MAX10 Multiplier	MAX10 PLL Guide MAX10 Multiplier Guide
28	W10 - C1	Debug	SignalTap Final Project Intro	SignalTap Reference
29	W10 - C2	NIOS II Intro	Nios II Processor Nios II Example	NIOS II Embedded Design Handbook NIOS II Processor Guide NIOS II Software Guide NIOS II Debug Guide
30	W10 - C3	NIOS II I/O	Nios II I/O
31	W11 - C1	NIOS II Character Buffer	Character Buffer Intro Character Buffer Hardware Character Buffer Software	Video IP Guide
32	W11 - C2	NIOS II Pixel Buffer	Pixel Buffer Intro Pixel Buffer Hardware Pixel Buffer Software	Embedded Peripherals Guide SDRAM Spec
33	W11 - C3	Accelerometer	Accelerometer Intro Accelerometer- NIOS Example	ADXL 345 (accelerometer) Spec
34	W12 - C1	MAX10 ADC	ADC Review Max10 ADC Max10 ADC - NIOS Example Max10 ADC - Toolkit Example	DE10 Lite ADC Warning MAX10 ADC Guide
35	W12 - C2	NIOS II Peripherals	Parallel I/O Interval Timer System ID	Embedded Peripherals - PIO Embedded Peripherals - Interval Timer Embedded Peripherals - System ID
36	W12 - C3	NIOS II Interrupts	Interrupts Interrupts Example	nios_interrupts_updown.c nios_interrupts_updown_2.c Exception Handlers
37	W13- C1	Serial Communications	SPI Review NIOS SPI Example	Embedded Peripherals - SPI
38	W13 - C2	Pipelining	Pipelining Pipelined SCP
39	W13 - C3		No class
40	W14 - C1	Project Work
41	W14 - C2	Project Work
42	W14 - C3	Project Work
43	W15 - C1	Test 2 Review	Test 2 Topics
44	W15 - C2	Project Work
45	W15 - C3	Test 2